Responsibilities:
- As part of Design team and to verify of digital design ,most on Serdes -PHY IP using UVM , including
1) Standard specification study/design feature study
2) Simple VIP (Verification IP) creation or third parity VIP survey
3) Verification plan define
4) Building sb/assertion check ,stimulus by constraint random
5) Create covergroup /assertion cover for functional coverage
6) Code coverage
7) Co –simulation with Analog PHY team
- Cross-department coordination and communication to drive project delivery on time