類比IC 設計工程師

IP design center of one International IC Design House

Responsibilities:

1. Responsible for High speed SerDes PHY design and will involved below diversified interface protocols e.g. USB4/USB 3.1, DP, PCI-E, MIPI C/D/MPHY, LPDDR4/5 PHY  
2. Cross-department coordination and communication to drive project delivery on time

Requirement :

1. At least five year of working experience with High-Speed Interface PHY development
2. Design experience in advanced CMOS technology.
3. Experienced/interested in one or multiple of Synopsys Astro/ICC, Cadence SOCE.
4. Interested in taking the challenges of 28nm and below physical designs

#semiconductor

#advancednode

#advancedtechnology

#SerDes

#highspeed

Contact: gary.cheng@adecco.com

MS degree with Engineer major (e.g. EE or CS) .