• 負責電源管理 或音訊IC 或 馬達驅動 (Gate Driver) IC 中的 類比電路設計以及 訊號模擬/測試
• 類比IC segmentation 專案管理
• 人員教育訓練

Responsibilities:

• As part of Design team and to verify of digital design ,most on Serdes -PHY IP using UVM , including  

1) Standard specification study/design feature study 

2) Simple VIP (Verification IP) creation or third parity VIP survey 

3) Verification plan define  

4) Building sb/assertion check ,stimulus by constraint random 

5) Create covergroup /assertion cover for functional coverage 

6) Code coverage 

7) Co –simulation with Analog PHY team    

• Cross-department coordination and communication to drive project delivery on time

Responsibilities:

1. Responsible for High speed SerDes PHY design and will involved below diversified interface protocols e.g. USB4/USB 3.1, DP, PCI-E, MIPI C/D/MPHY, LPDDR4/5 PHY  
2. Cross-department coordination and communication to drive project delivery on time

Serdes Design